1. Field of the Invention
The present invention relates to an Intel microprocessor-based computer system having a keyboard controller which generates gate-A20 and CPU RESET signals and further having control logic which generates the gate-A20 and CPU RESET signals in place of the signals generated by the keyboard controller. In particular, the present invention relates to a circuit which permits the control logic and the keyboard controller to both generate gate-A20 and CPU RESET signals for different operations of the computer system.
2. Description of the Related Art
Computer systems based upon the Intel microprocessor family which use the Microsoft DOS (disk operating system) operate in two modes referred to as "real mode" and "protected mode." The protected mode was developed when Intel expanded the addressing capabilities of the Intel 80286 microprocessor to be able to address more than 1 Megabyte (1,048,576 bytes) of memory. Prior to this expansion of the memory addressing capabilities, only 20 address bits were available to address memory. Thus, only address bits 0-19 were provided as outputs of the microprocessor. Many programs initially developed for systems using the earlier Intel microprocessors (e.g., the Intel 8088 microprocessor) relied on the absence of address bits above address bit 19. For example, some programs relied on the fact that when the memory addresses generated by the segment registers exceeded the addressing capability of the microprocessor, the addresses simply "wrapped around" to the lowest address. That is, address 100000.sub.HEX is the same as address 00000.sub.HEX in a 20-bit addressing system. Thus, when the new microprocessors having the additional address bits were developed, Intel also provided a real mode of operation in which the new microprocessors operated in a manner similar to the earlier microprocessors. As part of the real mode of operation, most computer systems block address bit 20 so that even if address bit 20 is activated by the microprocessor, address bit 20 is not provided to the memory system. Thus, the expected wrap around function is provided irrespective of the state of address bit 20.
In many of the first computer systems having real and protected modes, address bit 20 is controlled by a signal called gate-A20 (or gate20). Often, the gate-A20 signal was generated by a peripheral controller (e.g., a keyboard controller) which formed part of the overall computer system. The keyboard controller was frequently implemented as a microprocessor or microcontroller which monitored output signals from the system microprocessor (e.g., via a command output port 64.sub.HEX and a data input/output port 60.sub.HEX, hereinafter referred to as "port 64" and "port 60") and which generated keyboard control signals. The keyboard controller also provided scan codes signals representing keystrokes which were input on input/output port 60. For example, one commonly used keyboard controller still in use is an Intel 8042 keyboard controller. The structure of the basic 8042 keyboard controller has often been implemented as the core logic of a more complex peripheral controller circuit. Generally, the keyboard controller was also used to control the CPU RESET signal (also sometimes referred to as the CPU RESTART signal) because the CPU RESET signal was used in connection with the switching between the real mode and protected mode of operation.
Because the keyboard controller was implemented as a microprocessor, it executed internal instructions to monitor and receive commands and to generate signals. These instructions required time to execute. Thus, as the system microprocessors became faster, the time required by the keyboard controller to execute the internal instructions necessary to activate the gate-A20 signal and the CPU RESET signals became intolerable. In particular, the system microprocessor had to be programmed with delays, or the like, to allow time for the keyboard controller to recognize the commands and to generate the gate-A20 signal the CPU RESET signals before the system microprocessor executed instructions that relied on the signals being active and changing the configuration of the computer system 100. The programming of delays or other accommodations for the slow operation of the keyboard controller is considered an unacceptable programming practice because the delay times vary with different processor operating speeds. Furthermore, if the two signals are used frequently, the cumulative delays caused by the slow response of the keyboard controller caused a noticeable degradation in the operation of some computer systems.
Because of the perceived problems caused by the control of the gate-A20 signal and the CPU RESET signal, other ways of compensating for the slow operation of the keyboard controller were developed. In particular, additional logic has been included in more recent computer systems which monitors the same outputs of the system microprocessor. In one exemplary system, the additional logic operated independently of the keyboard controller in response to commands output from the system microprocessor on a port 92.sub.HEX (hereinafter "port 92"). The additional logic detects when commands are output on the port 92 to change the state of the gate-A20 signal or the CPU RESET signal, and the logic generates the two signals in place of the signals originally generated by the keyboard controller. Because the additional logic was implemented in hardware, the gate-A20 signal and the CPU RESET signal were generated much faster by the additional logic than they had been generated by the keyboard controller. Typically, because some application programs manipulated the keyboard controller directly to generate gate-A20 and CPU RESET, the keyboard controller continued to respond to the respective commands on port 64 to also generate the two signals.
An alternative apparatus described in U.S. Pat. No. 5,226,122 intercepts the keyboard controller signals on the output port 64, and, if the commands are directed to the control of either the gate-A20 signal or the CPU RESET signal, the apparatus blocks the commands from being received by the keyboard controller. Thus, the keyboard controller continues to operate as before, but the keyboard controller never receives the particular commands that manipulate the gate-A20 signal and the CPU RESET signal. Thus, the alternative apparatus generated the gate-A20 signal and the CPU RESET signal much faster than the keyboard controller would have generated the two signals.
In a further alternative, VLSI Technology developed a chipset which operates in response to both the port 92 commands and the port 64 commands directed to the generation of the gate-A20 signal and the CPU RESET signal. Thus, the VLSI Technology chipset is compatible with software which uses the port 64 commands through the keyboard controller to generate the two signals and is also compatible with software which uses the port 92 commands to control the two signals. Unlike the previously described apparatus, the VLSI Technology chipset does not block the port 64 commands to the keyboard controller. The keyboard controller continues to receive the port 64 commands from the system microprocessor and to generate the gate-A20 signal and the CPU RESET signal as before; however, the signal pins from the keyboard controller onto which the gate-A20 signal and the CPU RESET signal are output are not connected within the computer system. Thus, the gate-A20 signal and the CPU RESET signal are provided as outputs of the VLSI Technology chipset without the delay inherent in the keyboard controller and without any interference from the outputs of the keyboard controller.
It has been found however that there are situations where the gate-A20 signal and the CPU RESET signal generated by the keyboard controller are useful. For example, because the gate-A20 signal controls the ability to toggle address bit 20, it is necessary to be able to control the gate-A20 signal to enable memory accesses to locations having addresses above 1 Megabyte. In one particular example, certain computer systems, such as those produced by AST Research, Inc., the assignee of the present application, have FLASH BIOS which can be downloaded from a network, or the like. The FLASH BIOS is a non-volatile, writable memory that is accessed when the computer system is first booted when powered up or when re-booted in response to a reset. The software which downloads the FLASH BIOS from the network requires control of the gate-A20 signal to access memory above 1 Megabyte and requires control of the CPU RESET signal to initiate a restart of the system microprocessor after the downloading operation is complete; however, in conventional computer systems having the improved control logic discussed above, the gate-A20 signal and CPU RESET signal are strictly controlled by the operating system in accordance with the current mode of operation of the computer system (i.e., real mode or protected mode). In particular, operating systems, such as Windows NT and OS/2 monitor and trap outputs to port 92 or to port 64 which are directed to the manipulation of the gate-A20 signal or the CPU RESET signal. Attempts by an application program to manipulate one of the two signals via either output port result in errors which could result in the termination of the program attempting to manipulate either signal. Thus, a need exists for a system that permits the gate-A20 signal and the CPU RESET signal to be manipulated irrespective of the mode of the computer system so that operations which depend upon manipulation of the two signals, such as downloading of the FLASH BIOS, can be accomplished without resulting in system errors.